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flash memory 1 K9F1G08R0B K9F1G08R0B * samsung electronics reserves the right to c hange products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
flash memory 2 K9F1G08R0B document title 128m x 8 bit nand flash memory revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung elec tronics will evaluate and reply to your requests and questions about device. if you h ave any questions, please contact the samsung branch office near your office. revision no 0.0 1.0 1.1 1.2 remark advance final history 1. initial issue 1. edo mode timing is eliminated 2. copy-back program timing is eliminated 1. fbga package is added 1. tcs 31ns -> 25ns, treh 15ns -> 10ns draft date oct.30th, 2006 dec. 28th 2006 april 30th 2007 june 4th 2007
flash memory 3 K9F1G08R0B general description features ? voltage supply - 1.8v device(K9F1G08R0B) : 1.65v ~ 1.95v ? organization - memory cell array : (128m + 4m) x 8bit - data register : (2k + 64) x 8bit ? automatic program and erase - page program : (2k + 64)byte - block erase : (128k + 4k)byte ? page read operation - page size : (2k + 64)byte - random read : 25 s(max.) - serial access : 42ns((min.) 128m x 8 bit / 256m x 8 bit nand flash memory ? fast write cycle time - page program time : 200 s(typ.) - block erase time : 1.5ms(typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating-gate technology -endurance : 100k program/erase cycles ( with 1bit/512byte ecc) - data retention : 10 years ? command driven operation ? unique id for copyright protection ? package : - K9F1G08R0B-jcb0/jib0 : pb-free package 63 - ball fbga i (9 x 11 / 0.8 mm pitch) offered in 128mx8bit, the K9F1G08R0B is a 1g -bit nand flash memory with spare 32m-bi t. its nand cell provides the most cost- effective solution for the solid state application marke t. a program operation can be performed in typical 200 s on the (2k+64)byte page and an erase operation can be performed in typical 1.5ms on a (128 k+4k)byte block. data in the data register can be read o ut at 42ns cycle time per byte. the i/o pins serve as the ports for address and data i nput/output as well as command input. the on -chip write controller automates all program and erase functions including pulse repetition, where required, and internal verificatio n and margining of data. even the write-intensive systems can take advantage of the K9F1G08R0B extended reliability of 100k program/ erase cycles by providing ecc( error correcting code) with real time mapping-out algorithm. the K9F1G08R0B is an optimum solu- tion for large nonvolatile storage applicati ons such as solid state file storage and other portable applications requiring non- v o l a t i l i t y. product list part number vcc range organization pkg type K9F1G08R0B 1.65v ~ 1.95v x8 fbga
flash memory 4 K9F1G08R0B 63-ball fbga (measure d in millimeters) package dimensions 9.00 0.10 #a1 side view to p vi e w 1.00(max.) 0.45 0.05 4321 a b c d g bottom view 11.00 0.10 63- ? 0.45 0.05 0.80 x7= 5.60 11.00 0.10 0.80 x 5= 4.00 0.80 0.25(min.) 0.10max b a 2.80 2.00 9.00 0.10 (datum b) (datum a) 0.20 m a b ? 0.80 0.80 x11= 8.80 0.80 x 9= 7.20 65 9.00 0.10 e f h K9F1G08R0B-jcb0/jib0 r/b /we /ce vss ale /wp /re cle nc nc nc nc vcc nc nc i/o0 i/o1 nc nc vccq i/o5 i/o7 vss i/o6 i/o4 i/o3 i/o2 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c 3456 1 2 a b c d g e f h to p vi e w pin configuration (fbga) 2.00
flash memory 5 K9F1G08R0B pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and dat a, and to output data during read operations. the i/ o pins float to high-z when the chip is des elected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for comm ands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for addres s to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase operation. re read enable the re input is the serial data-out control, and when active drives the data onto t he i/o bus. data is valid trea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands , address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent program/erase protecti on during power transitions. the internal high volt- age generator is reset when the wp pin is active low. r/b ready/busy output the r/b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected.
flash memory 6 K9F1G08R0B 2k bytes 64 bytes figure 1. K9F1G08R0B functional block diagram figure 2. K9F1G08R0B array organization v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 12 - a 27 a 0 - a 11 command ce re we cle wp i/0 0 i/0 7 v cc v ss 64k pages (=1,024 blocks) 2k bytes 8 bit 64 bytes 1 block = 64 pages (128k + 4k) byte i/o 0 ~ i/o 7 1 page = (2k + 64)bytes 1 block = (2k + 64)b x 64 pages = (128k + 4k) bytes 1 device = (2k+64)b x 64pages x 1,024 blocks = 1,056 mbits page register ale 1,024m + 32m bit nand flash array (2,048 + 64)byte x 65,536 y-gating data register & s/a note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than required. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 *l *l *l *l 3rd cycle a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 4th cycle a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 row address row address column address column address
flash memory 7 K9F1G08R0B product introduction the K9F1G08R0B is a 1,056mbit(1,107,296,256 bit) memory organize d as 65,536 rows(pages) by 2,112x8 columns. spare 64x8 col- umns are located from column address of 2,048~2,111. a 2,112-by te data register is connected to memory cell arrays accommodat- ing data transfer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 32 cells that are serially connected to form a nand structure. each of the 32 cells resides in a different page. a block con sists of two nand structured strings. a nand structure consists of 32 cell s. total 1,081,344 nand cells reside in a block. the program a nd read operations are executed on a page basis, while the erase operation is executed on a block basis. the memory array consists of 1,024 separately erasable 128k-byte blocks. it indicates that the bit by bit erase operation is prohibited on the K9F1G08R0B. the K9F1G08R0B has addresses multiplexed into 8 i/os. this sc heme dramatically reduces pin counts and allows system upgrades to future densities by maintaining cons istency in system board design. command, address and data are all written through i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively , via the i/o pins. some commands require one bus cycle. for example, reset command, status read command, etc require just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. the 132m byte physical space requires 28 addresses, thereby requiring four cycles for addressing : 2 cycl es of column address, 2 cycles of row address, in t hat order. page read and page program need the same four address cycl es following the required command input. in block erase oper- ation, however, only the two row address cycles are used. device operations are selected by writing specific commands into the com- mand register. table 1 defines the sp ecific commands of the K9F1G08R0B. table 1. command sets note : 1. random data input/output can be executed in a page. caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st cycle 2nd cycle acceptable command during busy read 00h 30h read id 90h - reset ffh - o page program 80h 10h block erase 60h d0h random data input (1) 85h - random data output (1) 05h e0h read status 70h o
flash memory 8 K9F1G08R0B dc and operating characteristics (recommended operating cond itions otherwise noted.) note : 1. v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less. parameter symbol test conditions K9F1G08R0B(1.8v) unit min typ max operating current page read with serial access i cc 1 trc=42ns ce =v il, i out =0ma -1020 ma program i cc 2- erase i cc 3- stand-by current(ttl) i sb 1ce =v ih , wp =0v/v cc --1 stand-by current(cmos) i sb 2ce =v cc -0.2, wp =0v/v cc -1050 a input leakage current i li v in =0 to vcc(max) - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 input high voltage v ih (1) -0.8xv cc - v cc +0.3 v input low voltage, all inputs v il (1) - -0.3 - 0.2xvcc output high voltage level v oh i oh =-100 a vcc -0.1 -- output low voltage level v ol i ol =100ua - - 0.1 output low current(r/b )i ol (r/b ) v ol =0.1v 34 -ma recommended operating conditions (voltage reference to gnd, K9F1G08R0B-jcb0 : t a =0 to 70 c, K9F1G08R0B-jib0 : t a =-40 to 85 c) parameter symbol min typ. max unit supply voltage v cc 1.65 1.8 1.95 v supply voltage v ss 000v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during transit ions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum rating s are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data shee t. exposure to absolute maximum rating conditions for extended peri ods may affect reliability. parameter symbol rating unit 1.8v device voltage on any pin relative to vss v cc -0.6 to + 2.45 v v in -0.6 to + 2.45 v i/o -0.6 to vcc + 0.3 (< 2.45v) temperature under bias K9F1G08R0B-jcb0 t bias -10 to +125 c K9F1G08R0B-jib0 -40 to +125 storage temperature K9F1G08R0B-jcb0 t stg -65 to +150 c K9F1G08R0B-jib0 short circuit current i os 5ma
flash memory 9 K9F1G08R0B capacitance ( t a =25 c, v cc =1.8v, f=1.0mhz) note : capacitance is periodica lly sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. the device may include initial invalid blocks when first shi pped. additional invalid blocks may develop while being used. th e number of valid blocks is presented with both cases of inva lid blocks considered. invalid bloc ks are defined as blocks that contain one or more bad bits. do not erase or pro- gram factory-marked bad blocks. refer to the attached technical notes for appr opriate management of invalid blocks. 2. the 1st block, which is plac ed on 00h block address, is guaranteed to be a valid block up to 1k program/erase cycles with 1 bit/512byte ecc. parameter symbol min typ. max unit K9F1G08R0B n vb 1,004 - 1,024 blocks mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode hll hx read mode command input l h l h x address input(4clock) hll hh write mode command input l h l h h address input(4clock) l l l h h data input l l l h x data output x x x x h x during read(busy) xxxxxh during program(busy) xxxxxh during erase(busy) x x (1) x x x l write protect xxhxx 0v/v cc (2) stand-by ac test condition (K9F1G08R0B-jcb0 :ta=0 to 70 c, K9F1G08R0B-jib0:ta=-40 to 85 c K9F1G08R0B : vcc=1.65v~1.95v unless otherwise noted) parameter K9F1G08R0B input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load 1 ttl gate and cl=30pf
flash memory 10 K9F1G08R0B ac timing characteristics for command / address / data input notes : 1. the transition of the corresponding control pins must occur only once while we is held low 2. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle parameter symbol min max unit cle setup time t cls (1) 21 - ns cle hold time t clh 5-ns ce setup time t cs (1) 25 - ns ce hold time t ch 5-ns we pulse width t wp 21 - ns ale setup time t als (1) 21 - ns ale hold time t alh 5- ns data setup time t ds (1) 20 - ns data hold time t dh 5-ns write cycle time t wc 42 - ns we high hold time t wh 15 - ns address to data loading time t adl (2) 100 - ns program / erase characteristics note 1. typical program time is defined as the time within which mo re than 50% of the whole pages are programmed at 3.3v vcc and 25 c temperature . parameter symbol min typ max unit program time t prog - 200 700 s number of partial program cycles nop - - 4 cycles block erase time t bers -1.52 ms
flash memory 11 K9F1G08R0B ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5 s. parameter symbol min max unit data transfer from cell to register t r -25 s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 21 - ns we high to busy t wb -100 ns read cycle time t rc 42 - ns re access time t rea -30ns ce access time t cea -35ns re high to output hi-z t rhz -100ns ce high to output hi-z t chz -30ns ce high to ale or cle don?t care t csd 10 - ns re high to output hold t rhoh 15 - ns ce high to output hold t coh 15 - ns re high hold time t reh 10 - ns output hi-z to re low t ir 0-ns re high to we low t rhw 100 - ns we high to re low t whr 60 - ns device resetting time(read/program/erase) t rst - 5/10/500 (1) s re pulse width during busy state t rpb 35 - ns read cycle time during busy state t rcb 50 - ns re access time during busy state t reab - 40 ns
flash memory 12 K9F1G08R0B nand flash technical notes identifying initial invalid block(s) initial invalid block(s) initial invalid blocks are defined as blocks that contain one or more initial inva lid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is called the initial invalid block inform ation. devices with initial in valid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial invalid bl ock(s) does not affect the performance of valid bl ock(s) because it is isolated from the bi t line and the common source line by a sele ct tran- sistor. the system design must be able to mask out the initial in valid block(s) via address mappi ng. the 1st block, which is pl aced on 00h block address, is guaranteed to be a valid blo ck up to 1k program/erase cycles with 1bit /512byte ecc. all device locations are erased(ffh) except locations where the initial invalid block( s) information is written prior to shippi ng. the ini- tial invalid block(s) status is defined by the 1st byte in t he spare area. samsung makes sure that either the 1st or 2nd page o f every initial invalid block has non-ffh data at the column address of 2048. since the initial invalid block information is also era sable in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recogniz e the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(figure 3). any intentional erasure of t he original initial invalid block information is prohibited. * check "ffh" at the column address 2048 figure 3. flow chart to create initial invalid block table start set block address = 0 check "ffh" increment block address last block ? end no yes yes create (or update) no initial of the 1st and 2nd page in the block invalid block(s) table
flash memory 13 K9F1G08R0B nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes : if program operation r esults in an error, map out the block including the page in error and copy the target data to another block. * error in write or read operation within its life time, additional invalid bl ocks may develop with nand flash memory. refer to the qualification report for the a ctual data.the following possible failure modes shoul d be considered to implement a highly reli able system. in the case of status rea d fail- ure after erase or program, block replac ement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replacem ent can be executed with a page-si zed buffer by finding an erased empty block and reprogramming the current target data and copying t he rest of the replaced block. in case of read, ecc must be employed. to improve the efficiency of me mory space, it is recommended that the r ead or verification failure due to single bit error be reclaimed by ecc without any block replac ement. the said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read single bit failure ve rify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection
flash memory 14 K9F1G08R0B erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) write 30h block replacement * step1 when an error happens in the nth page of the bloc k ?a? during erase or program operation. * step2 copy the data in the 1st ~ (n-1)th page to the same location of another free block. (block ?b?) * step3 then, copy the nth page data of the block ?a? in the buffer memory to the nth page of the block ?b?. * step4 do not erase or program to block ?a? by creating an ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) { 1st (n-1)th nth (page) { an error occurs. 1 2
flash memory 15 K9F1G08R0B nand flash technical notes (continued) within a block, the pages must be programmed consecutively from the lsb(least significant bit) p age of the block to the msb(mos t significant bit) pages of the block. random page address programming is prohibited. in th is case, the definition of lsb page is the lsb among the pages to be programmed. therefore, lsb doesn't need to be page 0. from the lsb page to msb page data in: data (1) data (64) (1) (2) (3) (32) (64) data register page 0 page 1 page 2 page 31 page 63 ex.) random page program (prohibition) data in: data (1) data (64) (2) (32) (3) (1) (64) data register page 0 page 1 page 2 page 31 page 63 addressing for program operation : : : :
flash memory 16 K9F1G08R0B system interface using ce don?t-care. for an easier system interface, ce may be inactive during the data-loading or serial access as shown below. the internal 2,112byte data registers are utilized as separate buf fers for this operation and the system desig n gets more flexible. in addition, for v oice or audio applications whic h use slow cycle time on the order of -seconds, de-activating ce during the data-loading and serial access would provide significant sa vings in power consumption. figure 4. program operation with ce don?t-care. ce we t wp t ch t cs address(4cycles) 80h data input ce cle ale we data input ce don?t-care 10h address(4cycle) 00h ce cle ale we data output(serial access) ce don?t-care r/b t r re t cea out t rea ce re i/o 0 ~ 7 figure 5. read operation with ce don?t-care. 30h i/ox i/ox
flash memory 17 K9F1G08R0B note device i/o data address i/ox data in/out col. add1 col. add2 row add1 row add2 K9F1G08R0B i/o 0 ~ i/o 7 ~2112byte a0~a7 a8~a11 a12~a19 a20~a27 command latch cycle ce we cle ale command address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh ce we cle ale col. add1 t cls t cs t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t alh t ds t dh t wp i/ox i/ox col. add2 row add1 row add2 t wc
flash memory 18 K9F1G08R0B input data latch cycle ce cle we din 0 din 1 din final ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp i/ox * serial access cycle after read (cle=l, we =h, ale=l) re ce r/b dout dout dout t rc t rea t rr t rhoh t rea t reh t rea t coh t rhz i/ox t chz t rhz notes : transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. trhoh starts to be valid when frequency is lower than 33mhz.
flash memory 19 K9F1G08R0B status read cycle ce we cle re 70h status output t clr t clh t wp t ch t ds t dh t rea t ir t rhoh t coh t whr t cea t cls i/ox t chz t rhz t cs
flash memory 20 K9F1G08R0B read operation (intercepted by ce ) ce cle r/b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h read operation ce cle r/b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc row add2 30h t clr i/ox i/ox col. add1 col. add2 row add1 row add2 t coh t csd t csd
flash memory 21 K9F1G08R0B t clr random data output in a page ce cle r/b we ale re busy 00h dout n dout n+1 row address column address t wb t ar t r t rr t rc 30h 05h column address dout m dout m+1 e0h i/ox col. add1 col. add2 row add1 row add2 col add1 col add2 t whr t rea
flash memory 22 K9F1G08R0B m = 2112byte page program operation ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serialdata input command column address row address 1 up to m byte serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc i/ox co.l add1 col. add2 row add1 row add2 t adl notes : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t whr
flash memory 23 K9F1G08R0B page program operation with random data input ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serial data input command column address row address serial input program command read status command t prog t wb t wc t wc 85h random data input command column address t wc din j din k serial input i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 t adl t adl notes : 1. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. t whr
flash memory 24 K9F1G08R0B block erase operation ce cle r/b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc auto block erase setup command i/ox row add1 row add2 t whr
flash memory 25 K9F1G08R0B read id operation ce cle we ale re 90h read id command maker code device code 00h ech t rea address 1cycle i/ox t ar device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle K9F1G08R0B a1h 00h 15h 40h device 4th cyc. code 3rd cyc. 5th cyc.
flash memory 26 K9F1G08R0B 4th id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (w/o redundant area ) 1kb 2kb 4kb 8kb 0 0 0 1 1 0 1 1 block size (w/o redundant area ) 64kb 128kb 256kb 512kb 0 0 0 1 1 0 1 1 redundant area size ( byte/512byte) 8 16 0 1 organization x8 x16 0 1 serial access minimum 50ns/30ns 25ns reserved reserved 0 1 0 1 0 0 1 1 id definition table 90 id : access command = 90h description 1 st byte 2 nd byte 3 rd byte 4 th byte 5 th byte maker code device code internal chip number, cell type, number of simultaneously programmed pages, etc page size, block size,redundant area si ze, organization, serial access minimum plane number, plane size 3rd id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program between multiple chips not support support 0 1 cache program not support support 0 1
flash memory 27 K9F1G08R0B 5th id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (w/o redundant area) 64mb 128mb 256mb 512mb 1gb 2gb 4gb 8gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 reserved 0 0 0
flash memory 28 K9F1G08R0B device operation page read page read is initiated by writing 00h-30h to the command register along with four address cycles. after initial power up, 00h c ommand is latched. therefore only four address cycles and 30h command initia tes that operation after initial power up. the 2,112 bytes of data within the selected page are transferred to the data registers in less than 20 s(t r ). the system controller can detect the comple- tion of this data transfer(tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they may be read out in 42ns cycle time by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device output the data starting from the selected column address up to the last column address. the device may output random data in a page instead of the co nsecutive sequential data by writing random data output command. the column address of next data, which is going to be out, ma y be changed to the address which follows random data output com- mand. random data output can be operated multiple time s regardless of how many times it is done in a page. figure 6. read operation address(4cycle) 00h col. add.1,2 & row add.1,2 data output(serial access) data field spare field ce cle ale r/b we re t r 30h i/ox
flash memory 29 K9F1G08R0B figure 7. random data output in a page address 00h data output r/b re t r 30h address 05h e0h 4cycles 2cycles data output data field spare field data field spare field i/ox col. add.1,2 & row add.1,2 page program the device is programmed basically on a page basis, but it does allow multiple partia l page programming of a word or consecutiv e bytes up to 2,112, in a single page program cycle. the number of consecutive partial page prog ramming operation within the same page without an intervening erase operation must not exceed 4 ti mes for a single page. the addressing should be done in sequent ial order in a block. a page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by in putting the serial data input command(80h), followed by the four cycle address input s and then serial data loading. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address for the next data, which wi ll be entered, may be changed to the address which follows rando m data input command(85h). random data input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command(10h) initiates the programming process. writing 10h alone wit hout previously entering the serial data will not initiate the programming process. the internal write state controller automat ically executes the algorithm s and tim- ings necessary for program and verify, thereb y freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the status r egister. the system controller can detect the completion of a p ro- gram cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the p age program is complete, the write status bit(i/o 0) may be checked(figure 8). the internal write verify detects only errors for "1"s that are no t successfully programmed to "0"s. the com mand register remains in read status command mode until an other valid command is written to the command register. figure 8. program & read status operation 80h r/b address & data input i/o0 pass data 10h 70h fail t prog i/ox col. add.1,2 & row add.1,2 "0" "1" col. add.1,2
flash memory 30 K9F1G08R0B figure 9. random data input in a page 80h r/b address & data input i/o0 pass 10h 70h fail t prog 85h address & data input i/ox col. add.1,2 & row add1,2 col. add.1,2 data data "0" "1" figure 13. block erase operation block erase the erase operation is done on a block basis. bl ock address loading is accomplished in tw o cycles initiated by an erase setup c om- mand(60h). only address a 18 to a 27 is valid while a 12 to a 17 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasi ng process. this two-step sequence of se tup followed by execution command ensures t hat memory contents are not accidentally er ased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles er ase and erase-verify. when the erase operation is completed, the write status bit( i/o 0) may be checked. figure 13 details the sequence. 60h row add 1,2 r/b address input(2cycle) i/o0 pass d0h 70h fail t bers i/ox "0" "1" read status the device contains a status register whic h may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. af ter writing 70h command to the co mmand register, a read cycle outpu ts the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. th is two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 3 fo r specific status register definitions. the command register remains in status read mode until further commands are issued to i t. therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles. table 3. status register definition for 70h command note : 1. i/os defined ?not use? are recommended to be masked out when read status is being executed. i/o page program block erase read definition i/o 0 pass/fail pass/fail not use pass : "0" fail : "1" i/o 1 not use not use not use don?t -cared i/o 2 not use not use not use don?t -cared i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy busy : "0" ready : "1" i/o 7 write protect write protect w rite protect protected : "0" not protected : "1"
flash memory 31 K9F1G08R0B figure 18. read id operation ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea read id the device contains a product identification mode, initiated by wr iting 90h to the command register, followed by an address inp ut of 00h. five read cycles sequentially output the manufacturer code(e ch), and the device code and 3rd, 4th, 5th cycle id respective ly. the command register remains in read id mode until further commands are issued to it. figure 18 shows the operation sequence. figure 19. reset operation reset the device offers a reset feature, executed by writing ffh to t he command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. if the device is already in reset state a new reset command will be accepted by the command register. the r/b pin changes to low for trst after the reset command is written. refer to figure 19 below. ffh i/o x r/b t rst t whr t clr device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle K9F1G08R0B a1h 00h 15h 40h device 4th cyc. code ech 3rd cyc. 5th cyc. table 5. device status after power-up after reset operation mode 00h command is latched waiting for next command
flash memory 32 K9F1G08R0B ready/busy the device has a r/b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/b pin is normally high but transitions to low after pr ogram or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the internal contro ller has finished the operation . the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropriate value can be obt ained with the following reference chart(fig.20). its value can be determined by the following guidance. v cc r/b open drain output device gnd rp figure 20. rp vs tr ,tf & rp vs ibusy ibusy busy ready vcc voh tf tr vol 1.8v device - v ol : 0.1v, v oh : v cc -0.1v c l tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 1.70 1.70 1.70 1.70 1.70 0.85 0.57 0.43 rp(min, 1.8v part) = v cc (max.) - v ol (max.) i ol + i l = 1.85v 3ma + i l where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maxi mum permissible limit of tr
flash memory 33 K9F1G08R0B data protection & power up sequence the device is designed to offer protection from any involuntar y program/erase during power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 1.1v(1.8v device). wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 100 s is required before inter nal circuit gets ready for any command sequences as shown in figure 21. the two step co mmand sequence for program/erase provides additional software protection. figure 21. ac waveforms for power transition v cc wp high we 100 s 1.8v device : ~ 1.5v 1.8v device : ~ 1.5v
flash memory 34 K9F1G08R0B wp ac timing guide enabling wp during erase and program busy is progibited. the erase and program operations ar e enabled and disabled as follows: figure 18. program operation 1. enable mode 80h 10h we i/o wp r/b tww(min.100ns) 2. disable mode 80h 10h we i/o wp r/b tww(min.100ns) 1. enable mode 60h d0h tww(min.100ns) 2. disable mode 60h d0h tww(min.100ns) figure 19. erase operation we i/o wp r/b we i/o wp r/b

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